A FADC system has 24 ADC channels. Each channel has a VA chip and 128 strips. A data size of a strip is 10-bit. Thus, a strip needs a buffer of 2 bytes. Each channel generates data of 256 bytes and then a FADC system generates 6144 (24 x 256) bytes as an event.
There are 36 FADC systems for BELLE SVD2. A PC reads data from
minimum three FADC systems as a source node of the event builder.
Thus, 12 PCs are necessary for the link system.
Figure 
shows the configuration of
a PC and the Flash ADC systems.
Figure: Minimum configuration of FADC systems with a PC